ericmtzr
Occasional Contributor
3 years agoIntel PSG PCIe Cyclone V SX timing question
The customer is using either an Altera Cyclone part or a Critical Link board with Cyclone on it. This question came in from Critical Link regarding PCIe timing.
A customer use the MitySOM-5CSX SOM, and are wondering if they need to have a common reference clock between end points and root port for PCIe. Through Intel's docs I couldn't find a clear answer to this, I think my question can be summed up in the following:
Does the Cyclone V SX supports Separate Reference Clock No Spread Spectrum (SRNS) and/or Separate Reference Clock with Independent Spread Spectrum (SRIS)?