Forum Discussion
Altera_Forum
Honored Contributor
14 years agoInteger problem....
Hello.
I made the code below and that is working well. But when I test the code in Model_sim.... I don't know how to increase the input 1 by 1 like 0, 1, 2, 3, 4.... 15.. how can i make the inputs increase 1 by 1 in model_sim? I want to know the way!! LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY adder_integer is PORT( cin : in integer range 0 to 1; astring : in integer range 0 to 15; bstring : in integer range 0 to 15; sum_string : out integer range 0 to 31); end adder_integer; architecture arc of adder_integer is begin sum_string<= astring + bstring + cin; end arc;2 Replies
- Altera_Forum
Honored Contributor
you need a counter, so you need a clock input.
- Altera_Forum
Honored Contributor
It depends of how you write your testbench.
1. You can write a counter in your testbench in VHDL which feeds the input of "adder_integer" 2. You can write a macro macro_adder_integer.do (simple text file) which looks like :
And then in modelsim prompt, type do macro_adder_integer.do ModelSim Macros are in TCL langage 3. type force -freeze sim:/adder_integer/astring 0 10#0## increase "astring" from 0 to 15 for {set inc 0} {$inc <= 15} {incr inc} { # generate stimuli force -freeze sim:/adder_integer/astring 0 10#$inc# # simulate run 20 ns;# arbitrary value since you don't have clock in your design (typically 50Mhz) }run 20 ns
force -freeze sim:/adder_integer/astring 0 10#1#
run 20 ns
...
force -freeze sim:/adder_integer/astring 0 10#15#
run 20 ns :-D