Instruction on multiple clock cycle

Hi everyone !

I'm working on a project where I generate a timestamp through a counter that is incremented by 1 every clock cycle.

The thing is, every time I load the timestamp value in my buffer, the value is not incremented by 1 but by the size of my timestamp, which is 8 bits.

So I will have my first value at 0 and then the second value at 7 the third one at 15 and so on ....

I need to increment my counter no every clock cycle, but every 8 clock cycles, in order to solve the problem.

So i would like to know if such a thing is possible, and if so, how could I do it ?

I've tried to do it with a loop or with some wait statement, but so far nothing worked.

Here is the code of my counter :

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY counter IS

PORT(

clk_i : in std_logic;

count : out std_logic_vector(7 DOWNTO 0)

) ;

end counter;

ARCHITECTURE rtl OF counter IS

SIGNAL s_count : STD_LOGIC_VECTOR(7 DOWNTO 0);

begin

process (clk_i)

begin

if clk_i'event AND clk_i = '1' then

s_count <= s_count + 1;

end if;

end process;

count <= s_count;

end;

Hoping some of you can help !

Thanks in advance.

Cordially,

David.