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Honored ContributorInstantiating a black box in Quartus 2 Version 11
Hi all, I want to instantiate an entity as a black block (A friend will give me the VHDL description of this entity at a later stage) so that I can synthesize the part I have written. I am usin...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Try the attribute syn_black_box instead of black_box. to tzestan: black_boxes can be useful for exactly the OPs setup - synthesising a partial design to test resource usage, or design implementation. He's not trying to put it on an FPGA yet. Black boxes are often needed if a component comes from a netlist, not source code. --- Quote End --- Got it. Thanks.
