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Honored ContributorInstantiating a black box in Quartus 2 Version 11
Hi all, I want to instantiate an entity as a black block (A friend will give me the VHDL description of this entity at a later stage) so that I can synthesize the part I have written. I am usin...
Altera_ForumHonored Contributor
Honored ContributorQuartus is trying to synthesis logics. What do you want it to synthesize if not outputting constant level, given an empty box? The is no unknown (X) in real logics, it has to be either 0 or 1.
If want you mean is to retain unused logics, I don't understand why you want to do so. For example. an AND gate. If one input is at constant 0, the gate can be removed with output node driven 0 all time. Why would you want to retain the AND?
