Instantiate Max 10 ADC in VHDL

Ok, well you were right. I missed something subtle in the instantiation file because I was used to doing it the regular way.

Using component instead of entity fixed it:

U_ADC : component lsm_emulator_adc

port map (

adc_pll_clock_clk => ADC_Clock, -- adc_pll_clock.clk

adc_pll_locked_export => ADC_Locked, -- adc_pll_locked.export

clock_clk => SIM_Clock, -- clock.clk

command_valid => Command_Valid, -- command.valid

command_channel => Command_Channel, -- .channel

command_startofpacket => Command_SoP, -- .startofpacket

command_endofpacket => Command_EoP, -- .endofpacket

command_ready => Command_Ready, -- .ready

reset_sink_reset_n => Reset_n, -- reset_sink.reset_n

response_valid => Response_Valid, -- response.valid

response_channel => Response_Channel, -- .channel

response_data => Response_Data, -- .data

response_startofpacket => Response_SoP, -- .startofpacket

response_endofpacket => Response_EoP -- .endofpacket

);

I'm not sure if including the library made a difference or not. It's still in the HDL, but it may not be necessary. Thanks for the hint!