input to IIR filter in Verilog

You can't expect anything but "VERY noisy output" with 8 bit data length, particularly, when the ADC input level keeps a headroom. I don't understand the purpose of using such a low resolution. 12 bit would be fair, 16 bit standard CD audio quality.

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if I set "one_minus_a" to zero, I still have the input passing through the filter to the output

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Doesn't sound reasonable with the shown code.

Regarding the said application, a first order low-pass isn't a very selective filter.