input to IIR filter in Verilog

Thanks again Kaz!

Basically I want a filter that, for example, can attenuate 160Hz more so than 80Hz (second and first harmonics of E string respectively).

I was planning on expanding on the IIR code above to get an appropriate filter response to acheive this (so those values of "a" are just values to test with at this stage) - however that code is still giving me a VERY noisy output - something is not right.

Interestingly enough, if I set "one_minus_a" to zero, I still have the input passing through the filter to the output - how can this be?

module test_filter(clk,filter_in,filter_out);
parameter W=7;    // bit width - 1
parameter signed a=10'b0100000000; //256
parameter signed one_minus_a=11'b01100000000; //768
input   clk; 
input   signed  filter_in; 
output  signed  filter_out;
reg signed  y;
reg signed  x;
initial
begin
    x=0;
    y=0;
end
    
always@(posedge clk)
    begin
    x <= filter_in;
    y <= (one_minus_a*x) + (a*y);    // y=(1-a)*x+(a*y)
    end
        
assign filter_out=y;
endmodule  // test_filter