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BKB
Occasional Contributor
Occasional ContributorInput signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5
Hi, I am trying to interface the FTDI601 USB Bridge (https://ftdichip.com/products/ft601q-b/) to the Stratix 10 1SG10MHN3F74C2LG_U1/U2 FPGA on our design board. The reference clock for the interface...
BKBOccasional Contributor
Occasional ContributorHi Adiq,
I was able to sample the FTDI clock and other interface signals with high a 333.33 MHZ clock. The FTDI clock is 66mhz. I see the same behavior is RXF_N is asserted (low) earlier than when valid data is available. This is the same behavior I was seeing in earlier testing. i.e. RXF_N seems to be widened by a FTDI clock cycle. I have attached signaltap snapshot. for the initial input data coming from FTDI.
I am still working on changing the FTDI interface operation to be on negedge of ftdi clock at the input of FPGA..
Please review the attached signaltap snapshot and let me know any suggestions.
Best,
BB
