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Altera_Forum
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12 years ago

Input problem for PLL block

Hi Everyone, I am thinking using PLL for clock derivation,but I have a problem for PLL inputs.There are 11 inputs for PLL and I wanna use multiplexer (created in FPGA) before PLL to select one ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thanks Kaz and Alex ,

Yeah , they have same frequency but different phases , I didn't think about delay and now I guess It will be problem because the frequency is 10 MHz.It is seen that there is no clock selection unit (megafunctions , IP Core something like this ) to select and route for PLL.Then, I should find another solution .

Thanks again,

Best Regards,

İbrahim