Initial value setting error

Hello:

I'm new in verilog. Hopping that it's not a very stupid problem.

I'm tring to buid a FSM system using register "state" to perform the state now. There is no error hint or any functional problem on FSM insted of the initial problem on reg "state". The waveform shows that reg "state" keeping high at the begining, untill the stop signal arrives. Alought I had setting the initial value at begin, I can't fix it and I have no idea what could I do. Hopping that someone can help me.

Here is my code:

module state(start,stop,state);
input start,stop;
output reg state;

initial state = 1'b0;

always@(posedge start or posedge stop)begin
if(start == 1) state = 1;
else if(stop == 1) state = 0;
else state = state;
end
endmodule