New ContributorInfo (332102): Design is not fully constrained for setup requirements in max10 devices
Hi ,
I am using max10 device with espi slave ip in my project. My resource utilization is 98% and 97% sometimes .I am using pll of clock 100MHz using for espi controller logic in the design. I have constrained setup and hold with values 4 and 3 as I am using 25MHZ clock for generating 100MHZ clock.
Now the issue is espi reads/writes failes by giving "0xffffffff".Eventhough I am having the warning as Info (332102): Design is not fully constrained for setup requirements,the design works for one bit file. If I change the small logic and generate bit file it won't work. In-consistent behavior w.r.t compilation.
Can you please help me how to constrain the design with input and output delay constraints or is there any way to fix it.
create_clock -name clk -period 40 [get_ports {CPLD_25M_CLK}]
create_clock -name clk_espi` -period 30.3030303 [get_ports {CPU_CPLD_ESPI_CLK}]
create_clock -name clk_led` -period 100 [get_ports {LED_CLK}]
derive_pll_clocks
derive_clock_uncertainty
set_multicycle_path -from {espi_avmm_int:avmm_int|csr_addr*} -to {csr:csr|csr_rddata*} -setup -end 4
set_multicycle_path -from {espi_avmm_int:avmm_int|csr_addr*} -to {csr:csr|csr_rddata*} -hold -end 3
set_multicycle_path -from {csr:csr|csr_rddata*} -to {espi_avmm_int:avmm_int|avmm_writedata*} -hold -end 3
