inferred multiplier pipelining

Tricky is describing register retiming.

what about using the MegaWizard to create an lpm_multiplier, then looking at their multiplier instantion:

LIBRARY lpm;
USE lpm.all;
...
	lpm_mult_component : lpm_mult
	GENERIC MAP (
		lpm_hint => "MAXIMIZE_SPEED=5",
		lpm_pipeline => 3,
		lpm_representation => "SIGNED",
		lpm_type => "LPM_MULT",
		lpm_widtha => 20,
		lpm_widthb => 20,
		lpm_widthp => 40
	)
	PORT MAP (
		dataa => dataa,
		datab => datab,
		clock => clock,
		result => sub_wire0
	);

you can see the pipeline parameter here. it looks like its using the internal DSP block registers (i looked at RTL Viewer with an Arria II GX).