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Altera_Forum
Honored Contributor
12 years agoInfering DSP block in Arria V
Hello I'm trying to infer DSP blocks in my Arria V design as a replacement for my former ALTMULT_ADD instance in Stratix III. I notice that the input registers are placed outside (i.e. the DSP ...
Altera_Forum
Honored Contributor
12 years agoI put FvM's "unsigned_multiply_accumulate" unchanged into my design, added an additional register to the output datapath (to be sure to have no influence of the subsequent datapath elements), and let it run. Same result: The adder (accumulator) is outside the DSP block.
I noticed that the signal path goes directly from a_reg/b_reg to adder_out, but besides a longer path, I'd not expect influence on the mapping (no registering of multiplication output, although the signal is called 'mult_reg'). Is there any other setting I might have missed that prevents integrating the adder into the DSP block?