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Altera_Forum
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12 years ago

Infering DSP block in Arria V

Hello I'm trying to infer DSP blocks in my Arria V design as a replacement for my former ALTMULT_ADD instance in Stratix III. I notice that the input registers are placed outside (i.e. the DSP ...
Altera_Forum's avatar
Altera_Forum
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12 years ago

I tried to work with that (although it is already set to "auto" on global level), without success. I'm not able to bring the input registers into that DSP block. Furthermore, not even the accumulator is put in there. It's located outside.

Going back to the minimal version from the coding style manual (exactly using Qii51007/Example 13-7, but changed signal names for I/F purpose), I see the same behaviour. So it cannot be my enables, loads, etc. but muss be a different thing. I synthesized with timings at the edge or relaxed timing, no impact.

Any idea? Is there a different coding style required for Arria V or something else I missed?

P.S: The PROP_DELAY is a global constant (time := 1 ns) used for simulation purpose (had no influence anyway, as I took this out, too).