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Altera_Forum
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12 years ago

Infering DSP block in Arria V

Hello I'm trying to infer DSP blocks in my Arria V design as a replacement for my former ALTMULT_ADD instance in Stratix III. I notice that the input registers are placed outside (i.e. the DSP ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

try this on i/o registers:

attribute altera_attribute : string;

attribute altera_attribute of my_reg : signal is "-name auto_packed_registers normal"

BTW, I assume your aware that delay only applies to simulation(not synthesis)