inference of multipliers from VHDL

You may want to override the default behaviour by VHDL attributes, e.g. on an architecture level:

architecture rtl of my_design is
attribute multstyle : string;
attribute multstyle of rtl : architecture is "dsp";

Hello,

I'm not sure about the criteria that rule multiplier inference. But as long as the timing constraints are kept, there's no problem in using logic style multiplier, particulary with small word width. I hope, that Quartus changes to dsp style, if timing closure can't be achieved.

from your RTL Viewer image the circled multipler looks like it has a constant coefficient. this type of multiplier is built very efficiently in LE, it was probably a smart choice for Quartus to use them instead of a multiplier. you can always force a hard multiplier as mentioned.

Hello Pancake,