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Altera_Forum
Honored Contributor
Honored Contributorinference of multipliers from VHDL
Hello,
I am working with a Cyclone 2, she has many 8*8 multipliers. I have a module where I use multiplications. After compiling my VHDL code I can see with the "RTL Viewer" the multiplicators. But when I look the summary of the fitter I can see that my design does not use the embedded multipliers. So, how the FPGA is doing the multiplication, with LUT's? Why she does not use the embedded multipliers? Here I attach an image of the RTL. She is a bad girl "cyclone 2". Bye, thank you.5 Replies
Altera_ForumHello Pancake,
Yes, it was a multiplication with a constant. I forced the use of an embedded multiplicator (using the magic lines of FVM), but the timing according with the timer analyzer is worst. I guess, Quartus did a good election when doing it with LE instead using Embedded multipliers. Good Luck.- Altera_Forum
from your RTL Viewer image the circled multipler looks like it has a constant coefficient. this type of multiplier is built very efficiently in LE, it was probably a smart choice for Quartus to use them instead of a multiplier. you can always force a hard multiplier as mentioned.
- Altera_Forum
I'm not sure about the criteria that rule multiplier inference. But as long as the timing constraints are kept, there's no problem in using logic style multiplier, particulary with small word width. I hope, that Quartus changes to dsp style, if timing closure can't be achieved.
- Altera_Forum
Hello,
You are right, thank you. I added this two lines and now the multiplier is inferred. I have a question please. How was done the multiplication before add this two lines? Is better if I use the embedded multipliers I guess. Good Bye, and once again thank you. DABG - Altera_Forum
You may want to override the default behaviour by VHDL attributes, e.g. on an architecture level:
architecture rtl of my_design is attribute multstyle : string; attribute multstyle of rtl : architecture is "dsp";
