Independent clock mode True Dual port RAM in Agilex

I am sorry for the late reply.

I am using the fourth option from below for true dual port RAM (as I need all Port A ports to be clocked using one clock and Port B using a different clock)

• Single
• Dual clock: use separate ‘read’
and ‘write’ clocks
• Dual clock: use separate ‘input’
and ‘output’ clocks
• Customize clocks for A and B
ports

What I see is, a lot of ALMs is consumed for FIFO logic (60K ALM) in Agilex. I suppose this is due to the emulated TDP clock mode, while in Arria 10, TDP dual clock mode is natively supported and doesnt consume any ALM.

My question is, why is this mode not supported in Agilex. Is there a way I can realize separate clock for Port A and B of true dual port RAM without incurring such heavy ALM penalty.

Regards