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Altera_Forum
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12 years ago

Incorrect printline by using different memory segments

Hi! I have a system with NIOS and several memory blocks, 2 x On-Chip, SDRAM and SRAM. All of them work well, as long as I use same memory for all segments (.heap, .data, .stack....). As soon a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi!

Thank you, Sir, for the quick reply.

I'm very beginner, so sorry if my questions are stupid.

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Does your FPGA meet all timing specs?

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How can I find it out? Do I have to use TimeQuestAnalyzer? Never used it to be honest. I even get this critical warning

Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

and I read something about how to solve it but I don't know where to use the derive_clock_uncertainty command.

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Have you tried running the Memory tests on the different segments?

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You mean this Memory Test template in the Eclipse IDE? Realy no idea how things work, totaly beginner, sorry once more.:oops:

Regards.