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Altera_Forum's avatar
Altera_Forum
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16 years ago

including various design files

Hi all, I've created a couple of different design files for testing purposes and now want to combine all in one file, rather than writing them all out again. So I've created a new projec...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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I find it really tedious to write vhdl just for conneting blocks.

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There are more options than simply connecting blocks, e.g. generated structures and design variants. But whatever you prefer for your top design level, you need the component instantiation syntax to write structural VHDL code.