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Altera_Forum
Honored Contributor
Honored Contributorincluding various design files
Hi all, I've created a couple of different design files for testing purposes and now want to combine all in one file, rather than writing them all out again. So I've created a new projec...
Altera_ForumHonored Contributor
Honored ContributorI find it really tedious to write vhdl just for conneting blocks. Personally I like connecting blocks using schematics.You can generate symbols for your vhdl block easily: file->Create symbol. But of course its a matter of taste what you prefer.
