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Altera_Forum
Honored Contributor
16 years agoincluding various design files
Hi all, I've created a couple of different design files for testing purposes and now want to combine all in one file, rather than writing them all out again. So I've created a new projec...
Altera_Forum
Honored Contributor
16 years agoThe required method is component instantiation. The Quartus PDF tutorial for VHDL users or the Quartus VHDL templates shows the syntax. Also any VHDL text book.