In Cyclone V, is there other way to implement a transmitter PLL else than using CMU PLL?

​Hi Chee!

I have a look at the design. It is very helpful and solves my question. The top file is very informative.

Thank you very much!

I have one more question regarding the native PHY.

I usually do not use 'phase compensation FIFO' when I use custom PHY, because I connect the low speed parallel clock to the FPGA fabric interface clock/FPGA user-designed logic after the custom PHY. However, in the native PHY IP configuration window, I did not see a place to 'disable' the phase compensation FIFO. Is it always included? Does it do anything at all if I use the low speed parallel clock for FPGA fabric interface clock ?

Thank you!

Best regards,

Jue