In ARRIA10 device, if the LVDS data source is one clock plus 40 LVDS serial data bus, how to use the LVDS SERDES Intel IP?

Since the LVDS SERDES Ip has one constraint: all the RX channel should be placed in one IO bank, which has 24 RX channels in max, and they can only be clocked by the IO PLL resides in that IO bank. ...