Improve timing using multiple PLL

Question

Hello all,

In device like Cyclone V A9 there are 8 PLL. Generally I generate system clock from one PLL in normal mode but there is a way to improve timings using nearer PLL for some design parts using same system clock?

Thank you

altera_forum · Answer

I can better compensate remote locations with another PLL in sync with system clock?

altera_forum · Answer

Usually clock tree is global and if an improvement occurs due to multiple PLLs then it is likely a matter of chance fitting.

altera_forum · Answer

So just one PLL at time can be used and fitter chose the best?

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Improve timing using multiple PLL

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