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Altera_Forum's avatar
Altera_Forum
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15 years ago

Implementing ROM - which FPGA to use?

Hi all,

I need to implement 5 look-up tables (for 5 DACs), with a total of ~800Kbits.

I built a simple rom (didn't use a mega-function) - an entity with address and data pins and an internal array which has the data hardcoded inside. When I compiled the project I found that the FPGAs logic elements were almost entirely used (98%) but the memory bits weren't used at all. My questions are (sorry if they are too simple :) ):

1. What is the difference between logic elements and memory (in an FPGA)?

1. Why was my code tranlated into logic elements and not memory?

2. Is there a way to use the memory bits for the rom (instead or along with the logic elements)

Thanks in advance

11 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    FPGAs have dedicated blocks for memory (ASIC like sections) that you need to interface your logic fabric to it. It can be done by instantiation through megawizard (recommended for beginners) or inferred by special HDL templates (see Altera site).

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    So once I'll use a megawizard the rom will be mapped to the memory bits and not to the logic elements?

    Another (related) question: When I need to choose a flash memory for that project, how should I determine the flash size? Can I figure out the needed size from the compilation results?

    Thanks a lot
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    In the megawizard, you will have a choice (to choose which memory block size to choose from or set it auto if available,it also gives you entry for path to initial values or rom values i.e. a mif or hex file).

    What is that flash memory for? external for software? then it depends on your software size.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The flash is for configuring the FPGA. I'll burn it with ByteBlasterII. The FPGA code will be burned to that flash (including the rom that we discussed earlier).

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    In that case the size is fixed to every fpga irrespective of actual design size and you need to look at datasheet. Moreover you might need more than one image. In some cases compression/decompression could be considered. The flash is not necessary at testing stage as you can configure directly from pc (using sof)

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I'm am using a CycloneIII FPGA. CycloneIII supports different size flash memories. I intend to use a 16Mbit memory in a case that allows upgrade to 64Mbit. The board is being designed these days so I don't have much time for "virtual" tests. I won't use more then one image. My question is whether there is a way to know which flash memory should I use.

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    My question is whether there is a way to know which flash memory should I use.

    --- Quote End ---

    KAZ has answered the question clearly. The maximum configuration image size for each FPGA type is written in the device hardware manual. I guess, you intend to use serial flash (Altera EPCS or compatible), but you didn't explicitely tell. 16 MBit is good upto EP3C55, see table 9-3, configuration file size. Additional memory space may be required for designs involving soft processors.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Got it, thanks a lot. I suppose that if I was able to compile a specific project does it mean that it will certainly fit into the device that it was compiled for?

    In that case is there a way to know what size of flash would I need?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    An uncompressed configuration image will always require the size specified in device handbook. If you enable compression in the device configuration respectively in Programming File Conversion tool (for indirect JTAG programming), the required size will be reduced depending on the device utilization.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    dvidorot, back to your original question, a note (which probably you'll find out soon enough anyway):

    The RAM blocks in these FPGAs can only implement synchronous RAM and ROMs.

    So, a clock will be needed as well.