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Altera_Forum's avatar
Altera_Forum
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13 years ago

Implementing FFT on Chip

Hi There,

I'm currently trying to design a FFT system on my DE0-Nano board, reading values in from the ADC and outputting the complex representation of the output.

The ADC bit is all working correctly, but I'm having trouble implementing the FFT IP Core. I'm following the example found here: (http://www.alteraforum.com/forum/showthread.php?t=22862)

http://www.alteraforum.com/forum/showthread.php?t=22862

Unfortunately I'm not experienced enough to know how to implement this in my system correctly. What I really need is to be able to add the FFT component as a self contained object within my system schematic, with input pins for the clock source and the data in (to be taken from the ADC) and output pins for the complex and real parts of the output.

With the example I'm using, the input and output from the FFT core are two RAM blocks, can I remove these and just use GPIO so that I can connect to them from other parts of the system? If not, how do I write to them?

Any advice you can offer would be much appreciated.

Thanks

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Not that I know anything about that design but I suspect the RAMs are there to provide additional buffering to avoid underflow. This is common when you work with ADC or DAC devices that rely on fixed interval samples. So the RAMs (or FIFOs) let you output/accept data at irregular intervals without over/under flowing the off-chip devices.