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Altera_Forum
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13 years ago

Implementing FFT on Chip

Hi There, I'm currently trying to design a FFT system on my DE0-Nano board, reading values in from the ADC and outputting the complex representation of the output. The ADC bit is all wor...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Not that I know anything about that design but I suspect the RAMs are there to provide additional buffering to avoid underflow. This is common when you work with ADC or DAC devices that rely on fixed interval samples. So the RAMs (or FIFOs) let you output/accept data at irregular intervals without over/under flowing the off-chip devices.