Hi everyone, I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CAM (Content Addressable Memory) on a Cyclone-III FPGA. Can anyone help me with that? Thanks in advance Modellpilot

speak out ur deign spec such as 512x32bit,dual port,dual clock. In Quartus, it's easy to realize by using megawiard tool!

Sorry, but I think there is a missunderstanding: I'm looking for a CAM not for a RAM :cool: I allready had a look on Quartus. And Yes, the MegaWizard Plug-In Manager provides a lot of different memory controllers (single/dual-port, single/dual-clock, RAM/ROM/SREG). But CAMs are only supported when using an APEX device. When selecting a Cyclone-III CAMs and Flash Memory is disabled :mad: Modellpilot

What size do you want? What speeds? Is it Ternary(this is often a deal-breaker for larger CAMs, unless you don't mind using a ton of resources). There's a nice trick for making binary CAMs out of RAMs. I have a parameterized VHDL design for it, but I wrote it a few years ago and it targets either M4Ks or M512s. I can modify it for M9Ks, or might post-it as is for now, but am curious what your requirements are, as it might not work for you.

I need a 24x12 CAM (means 5-bit address and 12-bit word size). It would be great if you could help me with a VHDL code :) A version for M9Ks would be fine. But I think it is no big deal to adapt an example for M4Ks. Right? Thanks in advance!

An M9K can do a 32x8 CAM, so you'll basically change the parameters in M9K_CAM.vhd to do a 32x16 CAM(it needs to be a multiple of these dimensions), and then just tie off the extra ports. I built this quickly but believe it is correct. There is a presentation that is very old on this topic(it was done as Stratix was rolling out). I have a document that refers to it, so together you can use them for understanding. (Not the most professional delivery, but hey, if it works.) You can also just use the M9K_CAM.vhd and M9K.vhd files and just play with it yourself.

Implementing CAM (Content Addressable Memory) on Cyclone III

23 Replies

Altera_Forum
Honored Contributor
9 years ago
It should be RTL that can be synthesized for any family, except for the RAM. To be honest, I think altsyncram should work for Cyclone IV. Have you tried compiling?
If it errors out, then you would need to remove it and put in your own Cyclone IV RAM, whether it be a MegaFunction or inferring it, whichever you prefer.
Altera_Forum
Honored Contributor
9 years ago
Yes. it compiles by assigning the generics to the values from your code. Still wondering how you came up with these values. And about your code for CAM, the depth is 128 and the data bits is 16. I have just changed the width to 8 to have a 128 bytes of data.

--- Quote Start ---
It should be RTL that can be synthesized for any family, except for the RAM. To be honest, I think altsyncram should work for Cyclone IV. Have you tried compiling?
If it errors out, then you would need to remove it and put in your own Cyclone IV RAM, whether it be a MegaFunction or inferring it, whichever you prefer.
--- Quote End ---
Altera_Forum
Honored Contributor
9 years ago
Hello Again,

Is it possible to erase the used CAM completely for re-use?

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Implementing CAM (Content Addressable Memory) on Cyclone III

23 Replies

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