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Altera_Forum
Honored Contributor
Honored ContributorImplementing CAM (Content Addressable Memory) on Cyclone III
Hi everyone, I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CA...
Altera_ForumHonored Contributor
Honored ContributorI need a 24x12 CAM (means 5-bit address and 12-bit word size). It would be great if you could help me with a VHDL code :)
A version for M9Ks would be fine. But I think it is no big deal to adapt an example for M4Ks. Right? Thanks in advance!
