Implementing an asynchronous counter in a FPGA

Thank you for all the answers

The pulses are connected to comparators. The shape of the comparator output will look as follows:

- At low flow, ~400-ns-long pulses, spaced randomly apart from each other;

- At high flow, there is superposition of pulses. The comparator ouput is active most of the time, but I need to detect when it goes low. That represents a pulse of ~10-20 ns depending on rise/fall/propagation times of the comparator. The pulses are also random.

I attached the synopsis of the design that I have in mind. I understand that a 100-MHz system-clock domain with a synchronous counter would get the job done. But again, the design doesn't need to go that fast, and the power consumption is something I have to take into consideration.

Basically, the SPI interface is used at power-on once, then the counters are read every second and sent to the UI. The rest of the time, the design is "sleeping".

I'm still not really convinced that an asynchronous counter is a bad choice, unless the consumption difference is very negligible. But I guess it depends on the target device, which is not determined yet.

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you can probably use the pulse itself as clock input to set a flip-flop and then you use the system clock to sample and reset it.

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I am not sure I understood this part. Are you suggesting to use the pulse as clock for all the counter FFs? How about that using gray-code?

Damien