Implementing an asynchronous counter in a FPGA

The pulses are about 10-20-ns long, but nothing is sure until we actually make some tests on the board.

The thing that I forgot to mention is that the design is very small; basically 4 counters (4*32bits), a DAC interface (SPI), and a few logics. The counters are to be read every 1 sec, and I guess there is no need to go at 100MHz.

Does it make more sense?

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You could use the edge of one of the impulses as the clock input to a register in the FPGA and implement a ripple counter

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This is what I would like to try. In addition, I thought of gray code for robustness, but I had troubles trying to find an implementation for n bits. I made some researches about T-FF (made of D-FF + Mux) implementation but it did not lead to anything conclusive.

How would you start to solve this problem?

Thanks again

Damien