Implementing an asynchronous counter in a FPGA

You don't give us much information on what the 'impulsions' (impulses?) look like. How narrow are these pulses? Without knowing this it's a little difficult...

You could use the edge of one of the impulses as the clock input to a register in the FPGA and implement a ripple counter. Whilst the ripple-counter detailed in the paper you attached is perfectly valid, the FLEX 8000 series devices are certainly worth steering clear of - even if you can get hold of some. These old devices frequently implemented such ripple counters for resource efficiency. These devices also ran at much higher voltages too such that the EMC emissions (perhaps) needed more careful consideration than newer parts operating at lower voltages.

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I synchronize the counter with the system clock every second for example

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So you clearly need a system clock if you're to do this. But you imply it can't be 100MHz for EMC reasons - is that right? We regularly design with 'system' clocks at this and much higher frequencies. EMC certification is something all our products must go through. So, it's perfectly possible to design products with such an operating frequency.

If 100MHz is a suitable frequency to sample your impulses, then I recommend you consider doing that and using the same clock to drive a standard synchronous binary counter. Careful board and power supply design/layout should see you through any EMC certification - I hope.

Cheers,

Alex