Hello all, I'm trying to implement a table with stored switching angles for an inverter on to an FPGA. I'm a beginner so I'm having a lot of trouble figuring this out so please bare with me. Here's what I have: I have a .hex file, with 4608 lines representing 9 groups of 512 angles. So each angle has 512 increments depending on a modulation index starting from 0.48 to 1.00 in increments of 0.001. What i need to do is make a block that would store this table on to the FPGA and then when i give a modulation index as an input give 9 angles as an output depending on the modulation index. Is there a megafunction block I could use for something like this, or do i need to code it in VHDL? The FPGA i have at my disposal is a Cyclon III and also a Cyclon II training board. So please give me Your guidelines, suggestions and advises on how I could proceed with this. Any help would be appreciated greatly. Thank You.

This is going to be a look-up table (LUT) - this is just a ROM. It is basically a rom where you provide the address (modulation index) and you get the output data (angles) It is quite straight forward to code in VHDL and there are plenty of examples out there.

--- Quote Start --- This is going to be a look-up table (LUT) - this is just a ROM. It is basically a rom where you provide the address (modulation index) and you get the output data (angles) It is quite straight forward to code in VHDL and there are plenty of examples out there. --- Quote End --- Thank you, this was what i thought i needed to use as well. A follow up question though, do i need to use 9 of these blocks in parallel or can it all be done with one, and also how could I test the functionality of this (with a 7-segment display maybe as output)?

You could do it with 7 in parrallel or if you know the data rate is much less than your clock you can just pipeline it (ie. 1 request produces 9 clocks of results). Its up to you how you design it. But verifying with a 7 seg will be a bit of a chore. First of all verify the design in simulation with a testbench, then attach some communication core (like an RS232 port) so you can communicate with a PC.

--- Quote Start --- You could do it with 7 in parrallel or if you know the data rate is much less than your clock you can just pipeline it (ie. 1 request produces 9 clocks of results). Its up to you how you design it. But verifying with a 7 seg will be a bit of a chore. First of all verify the design in simulation with a testbench, then attach some communication core (like an RS232 port) so you can communicate with a PC. --- Quote End --- So I think I have finally figured out how to make the block. Any advice or tutorials on how to verify it in the testbench? Do I use ModelSim or something else, and if so which file do i open with ModelSim?

You need to create a testbench so you can drive stimulus into your block in modelsim. You compile all the files you need and simulate the testbench.

Implementing a table | Altera Community

11 Replies

Altera_Forum
Honored Contributor
10 years ago
This is going to be a look-up table (LUT) - this is just a ROM.
It is basically a rom where you provide the address (modulation index) and you get the output data (angles)

It is quite straight forward to code in VHDL and there are plenty of examples out there.
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
This is going to be a look-up table (LUT) - this is just a ROM.
It is basically a rom where you provide the address (modulation index) and you get the output data (angles)

It is quite straight forward to code in VHDL and there are plenty of examples out there.
--- Quote End ---

Thank you, this was what i thought i needed to use as well. A follow up question though, do i need to use 9 of these blocks in parallel or can it all be done with one, and also how could I test the functionality of this (with a 7-segment display maybe as output)?
Altera_Forum
Honored Contributor
10 years ago
You could do it with 7 in parrallel or if you know the data rate is much less than your clock you can just pipeline it (ie. 1 request produces 9 clocks of results).

Its up to you how you design it.
But verifying with a 7 seg will be a bit of a chore. First of all verify the design in simulation with a testbench, then attach some communication core (like an RS232 port) so you can communicate with a PC.
Altera_Forum
Honored Contributor
10 years ago
--- Quote Start ---
You could do it with 7 in parrallel or if you know the data rate is much less than your clock you can just pipeline it (ie. 1 request produces 9 clocks of results).

Its up to you how you design it.
But verifying with a 7 seg will be a bit of a chore. First of all verify the design in simulation with a testbench, then attach some communication core (like an RS232 port) so you can communicate with a PC.
--- Quote End ---

So I think I have finally figured out how to make the block. Any advice or tutorials on how to verify it in the testbench? Do I use ModelSim or something else, and if so which file do i open with ModelSim?
Altera_Forum
Honored Contributor
10 years ago
You need to create a testbench so you can drive stimulus into your block in modelsim. You compile all the files you need and simulate the testbench.
Altera_Forum
Honored Contributor
10 years ago
https://www.alteraforum.com/forum/attachment.php?attachmentid=11719

So I have this block made for implementation. Any advice on how to simulate this on a test board or SignalTap? Also do I need to add an input for the clock signal, if so from where?
Altera_Forum
Honored Contributor
10 years ago
Without a clock, it is not going to work.
The clock needs to come from an oscilator on the board.
Altera_Forum
Honored Contributor
10 years ago
Ok, I thought so. Any idea what name I can find that clock under?
Do I just connect an input to the clock and then assign that input to a certain pin number?
The board model that i am using is Cyclone™ II FPGA EP2C70F672-C6

And regarding the inputs and outputs, any recommendations on what I could connect them to actually test the block?
Altera_Forum
Honored Contributor
10 years ago
The clock will be a device on the board, not inside the FPGA.
Assuming its a standard altera/terasic dev board, the reference manual should tell you what clocks are on the board and what pins they are connected to on the FPGA.
Altera_Forum
Honored Contributor
10 years ago
Excuse my bad knowledge, I am fairly new to FPGAs. In the picture bellow is a screenshot of the user manual regarding the on board clock. So to try this again, how do I lead a signal from this clock output, to the input of the RAM block? Do I put a line of code in VHDL code, or do I use block that i connect to something. I am sorry if its a dumb question but I really don't understand how to do it.
https://www.alteraforum.com/forum/attachment.php?attachmentid=11720

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Implementing a table

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