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You could do it with 7 in parrallel or if you know the data rate is much less than your clock you can just pipeline it (ie. 1 request produces 9 clocks of results).
Its up to you how you design it.
But verifying with a 7 seg will be a bit of a chore. First of all verify the design in simulation with a testbench, then attach some communication core (like an RS232 port) so you can communicate with a PC.
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So I think I have finally figured out how to make the block. Any advice or tutorials on how to verify it in the testbench? Do I use ModelSim or something else, and if so which file do i open with ModelSim?
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