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Altera_Forum
Honored Contributor
Honored ContributorImplementing 18-bit lvds serializer in CPLD
Hello,
Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-bit LVDS deserializer on a low cost FLASH CPLD. For a projet I need the deserializer and some simple glue logic. It would be perfect if this could be implemented in an all-in-one chip like one out of the MAX family. However, I am not sure about the clock recovery part. This probably needs a PLL of some sort. Can this be done in a MAX? Thanks in advance for any help. Ronald12 Replies
Altera_ForumThe problem is matching the edges of the clock signal to the stable points in the data stream.
- Altera_Forum
Aha, so you would need a PLL anyway. I am not sure how to proceed now. The simplest way would be to use the sensors parallel output. Als this is a stereovision camera I would need to synchronize two parallel datastreams into one wider stream. This is probably easier to do low cost than using the serial data. It only limits the cable length considerably.
Does a Cyclone specified for 275Mhz also take signals up to 275Mhz on the pins? In that case I might still be able to run it at half speed.
