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Altera_Forum
Honored Contributor
Honored ContributorImplementing 18-bit lvds serializer in CPLD
Hello, Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-...
Altera_ForumHonored Contributor
Honored ContributorThe problem is matching the edges of the clock signal to the stable points in the data stream.
