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What's the intended bit rate? Low cost FPGA (Cyclone series) neither have a decicated clock recovery hardware, but CDR can be implemented for medium bit rates utilizing PLL dynamic phase shift or oversampling with multiphase clocks.
MAX II/V is the only Flash FPGA available from Altera. It's named CPLD according to the low logic element count , but actually using SRAM FPGA technology.
P.S: I assume the bit rate is 450 MHz, 18*25 MHz?
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Yes, no that you mention it. This is the bitrate. I never thought of it that way. I guess the last time I looked at this was before I had my morning coffee. It is an image sensor interface. The image sensor runs om 25Mhz, but it has an internal PLL to generate the bit clock. This does mean that the working clock is quite high for a low cost part.
I might still get away with using a lower clock rate (eg. 14.7Mhz), but the resulting bit clock will still be rather high.
What is considered to be a medium bit rate?
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