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I will leave the tool free to implement and would rather focus on my required outputs. In fact there are no silicon level gates and no dedicated muxes in FPGAs but just LUTs + registers.
All logic is finally a network of luts connected together plus registers in between. We trust the tool or we won't be here.
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Yes, the thing is I am doing a mixed signal simulation and I have a standard 2:1 Mux available and it is really easy to design a 2:1 Mux.
Now, the logic gives me a decoder with OR gates whose transistor level is difficult to design.
Thus, if there would have been a tool that gave me the Mux equivalent logic, I could easily implement it at a transistor level.
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