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Hii Everyone,
I am using Quartus Prime Design suite 15.1.
I wrote a behavioral verilog code. When I compile it and see its netlist using Tools->netlist viewer->RTL viewer, I see the code is realized using some random gates and decoder logic.
I wanted to implement the logic only using 2:1 Mux. Is there any setting to do that.
Thank you,
Surya
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I will leave the tool free to implement and would rather focus on my required outputs. In fact there are no silicon level gates and no dedicated muxes in FPGAs but just LUTs + registers.
All logic is finally a network of luts connected together plus registers in between. We trust the tool or we won't be here.
Honored Contributor
