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What is the point of doing something in VHDL/Verilog that is not synthesizable?
Sorry i can't help because i've never used VHDL to interpret a file, but the hex part are just bits, you can compare them to other bits that have a meaning and see the info on the file..
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Many reasons - testbenches, Models and things like that. There is a large part of VHDL that is unsynthesisable (file IO, pointers, protected types etc).
Mucahid - You need to run this code in modelsim - not quartus. the simulator in quartus (and is only available in older versions of quartus, it was dropped in V10) is very basic and requires that you synthesise the code befoer you can simulate. Because the code is unsynthesisable there is the problem. You need to run it in modelsim.
Secondly - there is no type "hex_image_file" declared - hence the error. You need to delcare the type yourself.
thirdly - this file is using very old syntax (VHDL 1987). I suggest using VHDL 93. VHDL is very good at reading text files but not good at reading anything else.
I suggest reading a textio tutorial online
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