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Honored Contributor
Honored ContributorIllegal Parameters in ALTGX megafunction
Hi,
I am implementing a PCIE design on Stratix 4 GX using ALTGX megafunction. The synthesis runs ok, but the fitter gives following errors +-----------------+ ; Fitter Messages ; +-----------------+ Info: ******************************************************************* Info: Running Quartus II Fitter Info: Version 9.0 Build 132 02/25/2009 SJ Full Version Info: Processing started: Wed Apr 29 15:40:32 2009 Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off PCIE -c PCIE Info: Parallel compilation is enabled and will use 2 of the 2 processors detected Info: Selected device EP4SGX230KF40C2ES for design "PCIE" Info: Core supply voltage is 0.9V Info: Low junction temperature is 0 degrees C Info: High junction temperature is 85 degrees C Error: The "GXB PLL" parameter "charge_pump_current_bits" is set to an illegal value of "10" on atom "altgx_io:altgx_io_inst|altgx_io_alt4gxb_q8ob:altgx_io_alt4gxb_q8ob_component|tx_pll_alt0" File: C:/Altera_Projects/PCIE/altgx_io.v Line: 767 Info: No legal values found Error: The GXB PLL "CMU" parameter "input_clock_frequency" is set to an illegal value of "100.0 MHz". The value is illegal when the device speed grade is "2", the parameter "base_data_rate" is set to "2500.0 Mbps", and the parameter "Pll Type" is set to "CMU" on atom "altgx_io:altgx_io_inst|altgx_io_alt4gxb_q8ob:altgx_io_alt4gxb_q8ob_component|tx_pll_alt0" File: C:/Altera_Projects/PCIE/altgx_io.v Line: 767 Info: "312.5 MHz to 312.5 MHz" is a legal range Info: "250.0 MHz to 250.0 MHz" is a legal range Info: "156.25 MHz to 156.25 MHz" is a legal range Info: "125.0 MHz to 125.0 MHz" is a legal range Info: "78.125 MHz to 78.125 MHz" is a legal range Info: "62.5 MHz to 62.5 MHz" is a legal range Info: "50.0 MHz to 50.0 MHz" is a legal range Info: "625.0 MHz to 625.0 MHz" is a legal range Info: "500.0 MHz to 500.0 MHz" is a legal range Info: "200.0 MHz to 200.0 MHz" is a legal range Info: "400.0 MHz to 400.0 MHz" is a legal range Error: The "GXB PLL" parameter "loop_filter_r_bits" is set to an illegal value of "1600" on atom "altgx_io:altgx_io_inst|altgx_io_alt4gxb_q8ob:altgx_io_alt4gxb_q8ob_component|tx_pll_alt0" File: C:/Altera_Projects/PCIE/altgx_io.v Line: 767 Info: No legal values found Error: The "GXB PLL" parameter "m" is set to an illegal value of "1". The reference clock frequency to the PLL PFD (phase-frequency detector), which is input_clock_frequency ("100.0 MHz") \ n ("1"), must be the same as the feedback frequency to the PLL PFD, which is base_data_rate ("2500.0 Mbps") \ 2 \ m on atom "altgx_io:altgx_io_inst|altgx_io_alt4gxb_q8ob:altgx_io_alt4gxb_q8ob_component|tx_pll_alt0" File: C:/Altera_Projects/PCIE/altgx_io.v Line: 767 Info: No legal values found Error: The "GXB PLL" parameter "n" is set to an illegal value of "1" on atom "altgx_io:altgx_io_inst|altgx_io_alt4gxb_q8ob:altgx_io_alt4gxb_q8ob_component|tx_pll_alt0". The value of n is restricted based on the min and max reference clocks to the PLL PFD (phase-frequency detector) for the speed grade of 2 and the specific Pll Type of "CMU". For non-basic protocol configurations, the value of N is fixed. File: C:/Altera_Projects/PCIE/altgx_io.v Line: 767 Info: No legal values found Error: Pll Type is set to an illegal value "CMU" on node altgx_io:altgx_io_inst|altgx_io_alt4gxb_q8ob:altgx_io_alt4gxb_q8ob_component|tx_pll_alt0 File: C:/Altera_Projects/PCIE/altgx_io.v Line: 767 Info: No legal values found Error: Quartus II Fitter was unsuccessful. 6 errors, 0 warnings Error: Peak virtual memory: 275 megabytes Error: Processing ended: Wed Apr 29 15:40:36 2009 Error: Elapsed time: 00:00:04 Error: Total CPU time (on all processors): 00:00:03 Any help is appreciated Thanks, Akshay
