Forum Discussion
6 Replies
- Altera_Forum
Honored Contributor
--- Quote Start --- I want to use the FPGA to realize the goal of high speed counter,which can count 10G pulse per second. Would you please tell me which series of the altera can make it ? How to realise this goal ?thank you. --- Quote End --- So, the first question is purely limitations-- are you looking at, in realtime, counting pulses that are at 10 GHz? You're basically entering RF land or major over-sampling, or you're looking at doing something with high-speed transceivers to convert a 10G signal in to something going slow enough that it can be processed. In short, what are you looking for? A counter? A transceiver to send signals? An RF system? or something else all together? http://hackaday.com/2014/06/29/counting-really-really-fast-with-an-fpga/ You can sample a faster signal to get an idea and do processing, but I at least would need more information to figure out what is going on. Just saying a 10G counter really isn't enough because, in short, I think there is only one chip out there that can even run at a 10 GHz clock speed, and I don't think it's in the general market. - Altera_Forum
Honored Contributor
Generally the Stratix V series transceiver can run at 10Gbps data rate and above. Note that this is only at transceiver. The core speed would be much lower. You can check the datasheet for detail.
- Altera_Forum
Honored Contributor
I use it for counter,not for transceiver to send signals.Can it realize this ?
- Altera_Forum
Honored Contributor
I don't think so. Even with latest upcoming Stratix 10 device, the FPGA core can go up to 1GHz only.
- Altera_Forum
Honored Contributor
--- Quote Start --- I don't think so. Even with latest upcoming Stratix 10 device, the FPGA core can go up to 1GHz only. --- Quote End --- In 2000 the highest fpga practical speed was sort of 100MHz. Now 10 times higher and so if we interpolate we might reach 10 GH in 2030. I doubt I can wait that far or live that long. Can you try see if parallel processing helps? - Altera_Forum
Honored Contributor
Ok, I am thinking something like performing clock slicing using PLL. For example, if the FPGA core is running at 200MHz, you will need to slice 50 times to get 10GHz. In this way you need to create 50 clocks with phase shifted by 7.2 degrees each to achieve the 10G pulse sampling rate.