Forum Discussion
Altera_Forum
Honored Contributor
10 years agoOk, I am thinking something like performing clock slicing using PLL. For example, if the FPGA core is running at 200MHz, you will need to slice 50 times to get 10GHz. In this way you need to create 50 clocks with phase shifted by 7.2 degrees each to achieve the 10G pulse sampling rate.