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Bill_A's avatar
Bill_A
Icon for New Contributor rankNew Contributor
3 years ago

I2C to Avalon-MM Master Bridge

I have used Platform Designer in Quartus Prime Lite 20.1.1 Build 720. This bridge is connected to multiple I2C Master cores. There is no address overlap in Platform Designer. The Master uses 3 byte addressing with no address stealing. This worked fine with a MAX10 device using version 18.1 The new Cyclone IV GX design has problems. The core addresses are offset by 0x100. The problem is that after the last core, the Avalon-MM steers the transaction to the first interface. For Example,

I2C0 is at 0x000

I2C1 is at 0x100

I2C2 is at 0x200

I2C3 is at 0x300

I2C4 is at 0x400

I2C5 is at 0x500

If an access is made at 0x600, or 0x700, or 0x800, the Avalon Bridge sends it to the registers at the 0x100 offset.

2 Replies

  • Bill_A's avatar
    Bill_A
    Icon for New Contributor rankNew Contributor
    3 years ago

    I managed to get it to work. I needed to set


    Automate default slave insertion

    to TRUE in Platform Designer.

    I would like to know why the behavior is so different for the same qysy implementation with different FPGA families. The MAX10 had this set to FALSE and behaves quite differently.

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    3 years ago

    Glad to hear that your issue has been resolved.


    Actually there are two methods to specify default slave:

    • <Automatic setting method> Automate default slave insertion to TRUE
    • <Manually> Right-click the bar in System Contents of Platform Designer to display and select Default slave

    May be you are using second method for MAX 10.

    Let me know if you have any further updates or concerns.


    Best Regards

    Sheng