I2c through FPGA not working on Cyclone V SoC Terasic DE1SoC board

Dear Nalkhateeb,

no, I'm not starting with GHRD. I like using schematic as a top level entity and all examples are top level textual.

Preloader is configuring registers in processor, so probably without changing it, it wouldn't work. If You want to use peripherals via FPGA fabric, the internal mux register needs to be set accordingly by preloader.

You can doublecheck see how this registers are set with devmem linux command.

Next thing is the correct connection of IOs to signals in QSys entity. I had connection problems probably because I have changed version of Quartus in the meantime an it was incompatible. As far as i remember, in older versions I2C could be master only/slave only/full, and now it can be only full. Pay attention to connectionss.

I could also recommend to update timing parameters of i2c driver in devicetree. Default timing parameters failed for some of my slave devices. Some worked, some not. Some slave device was unable to signal the ACK. It looked like HPS was not issuing High-Z to pin in correct time. Here is my i2c device tree entry with overwritten timings that worked for me:

	hps_i2c1: i2c@0xffc05000 {
			compatible = "snps,designware-i2c-17.0", "snps,designware-i2c";
			reg = <0xffc05000 0x00000100>;
			interrupt-parent = <&hps_arm_gic_0>;
			interrupts = <0 159 4>;
			clocks = <&l4_sp_clk>;
			emptyfifo_hold_master = <1>;	/* embeddedsw.dts.params.emptyfifo_hold_master type NUMBER */
			status = "okay";	/* embeddedsw.dts.params.status type STRING */
			clock-frequency = <100000>;
			i2c-sda-hold-time-ns = <100>;
			i2c-sda-falling-time-ns = <100>;
			i2c-scl-falling-time-ns = <300>;
		}; //end i2c@0xffc05000 (hps_i2c1)