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Altera_Forum
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15 years ago

I2C slave in Cyclone II device

Hi, I have written a simple I2C slave receiver in vhdl that I want to put in a cyclone II device. It is asynchronous and detects start and stops and device address + Rd/Wr and subadress. If...
Altera_Forum's avatar
Altera_Forum
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15 years ago

There may be a particular timing problem with your asynchronous processing or a problem with the SCL waveform, that possibly causes double clocking at the edges. Generally you'll hardly achieve the specified glitch tolerance for the I2C lines with an asynchronous design without external signal filtering and schmitt-trigger gates. It would be much more simple to do it synchronously with a clock.