I have too often read how made Asynchronous signals e.g clear, set e.t.c are but than

Just to ad to what Rysc pointed at. Async design is a completely different digital methodology (I believe it preceded synchronous design historically).

The FPGA design is meant to be synchronous i.e. clouds of combinatorial logic inserted between registers (RTL chain) though some signals entering the chain may be stray (asynchronous) coming off chip or internally from different clock domain. One can view these stray signals as the unwanted inevitable headache left over from asynch methodology. The fpag designer must make efforts to tackle these troublesome signals.

Going back to asynch method for FPGAs is a dream so far and will make good money if you find a trick.