I have too often read how made Asynchronous signals e.g clear, set e.t.c are but than

No problem. I do think we're using "asynchronous logic" in too broad of a sense, as it encompasses everything from an asynch clear(found in most designs) to a completely asynchronous Achronix design, along with many cases in between. (Another case I've seen is the "asynchronous bus/fabric", whereby the individual processing blocks are synchronous, but they send data to other blocks asynchronously, so there's no real logic being done, just data being transferred). I've always been curious how truly asynchronous logic works. The best I've found is that a feedback loop is generated, so data goes out and is processed, and when it's done being processed, the feedback signal states that new data can enter the loop. Because of this, there is no clock, just all these loops. One really nice thing is that they run as fast as the silicon runs, where synchronous designs have a clock that has been throttled to the slowest path under the slowest PVT conditions. But if you need a guaranteed throughput, I'm not sure how asynchronous design gets around that. Anyway, if there's someone out there who has a good grasp of it, I'd be interested in hearing more...