I have too often read how made Asynchronous signals e.g clear, set e.t.c are but than

Mankind resorted to clocked synchronous approach because they could not control logic hazards of non-clocked design(asynch). Asynch design can be very fast as it has no registers to worry about their timing violation. It is only but seriously limited by variable delays at various levels of logic.

The drawback of clocked design is the register timing bottleneck which mankind is converging towards with clock speeds as high as 500MHz in fabric and much more in ASICs. The other drawback is forgetting that in FPGAs and designing everything combinatorial. If you google "Achronix" you will see they want to build an hyperfast fpga based on no clocks but appear to the fpga designer as any clocked design i.e. you design as usual but the tool will convert it to asynchronous and you don't worry about setup/hold timing(sorry Rysc).